This invention relates to a silicon-on-insulator(SOI) device, and more particularly to a SOI device with a reversed stacked capacitor cell and a body contact structure.
With high performance of semiconductor devices, the semiconductor integration technology using SOI wafers in stead of bulk silicon wafer, which has a stack structure of a base substrate for supporting means, a semiconductor layer for providing an active layer and a buried oxide interleaving therebetween, has been proposed. It is because the devices fabricated in the SOI wafer have advantages of high performance due to low junction capacitance, low voltage driving due to low threshold voltage and decrease in latch-up due to complete device isolation, as compared with those fabricated in the bulk silicon wafer.
On the other hand, because high integration of memory devices such as DRAMs accompanies reduction in cell dimension, it is inevitably necessary to increase height of a capacitor in order to improve capacitance. However, increase in height of a capacitor causes global topology and then increases the height in a metal contact hole of a peripheral region so that it has a difficulty in process and it causes metal interconnection to be open.
So as to solve the above problems, a SOI device having a reversed stacked capacitor(RSC) cell structure is proposed, which forms a capacitor in one surface of a semiconductor layer, reversely turns over the semiconductor layer and then carries out the following process for a bit line and a metal interconnection in another surface of the semiconductor layer.
FIG.1A to FIG.1C are sectional views for illustrating a method for fabricating a SOI device with a RSC cell in the prior art. Referring to FIG.1A, a semiconductor substrate 1 having a cell region CR and a peripheral region PR is prepared. An isolation film 2 of a trench type is formed in one surface of the semiconductor substrate 1. Gates 4 including gate oxides 3 are formed in device formation regions of the cell region CR and the peripheral region PR of the semiconductor substrate 1 which are defined by the isolation film 2. Spacers 5 are formed at the both sides of the gates 4 and first source and drain regions 6a and 7a and second source and drain regions 6b and 7b which are lightly doped drain structures are formed in the device formation regions of the cell region CR and the peripheral region PR at the both sides of the gates 4, respectively. A first insulating layer 8 is formed over the one surface of the semiconductor substrate 1 to cover the gates 4.
Referring to FIG. 1B, a contact hole 9 for storage node is formed in the first insulating layer 8 to expose the first source region 6a which is formed in the cell region CR of the semiconductor substrate 1. A capacitor 10 is formed over the first insulating layer 8 to be contacted with the first source region 6a through the contact hole 9 for storage node. The capacitor 10 includes a storage node 10a, a dielectric film 10b and a plate node 10c. A second insulating layer 11 is formed over the first insulating layer 8 to cover the capacitor 10 and then a base substrate 20 is bonded on the second insulating layer 11.
FIG.1C is a sectional view where the bonded base substrate 20 and the semiconductor substrate 1 are reversely turned over and then the following processes has been carried out. Another surface of the 30 semiconductor substrate 1 is etched to expose the isolation film 2, so that a semiconductor layer 1a is obtained. A third insulating layer 21 is formed over the semiconductor layer 1a and then etched to form a bit line contact hole 22, thereby exposing the first drain region 7a in the cell region CR. A bit line 23 is formed over the third insulating layer 21 to be contacted with the first drain region 7a through the bit line contact hole 22.
A fourth insulating layer 24 is formed over the third insulating layer 21 to cover the bit line 23 and then the third and fourth insulating layers 21 and 24 are etched to form a first and a second metal contacts 25 and 26 thereby exposing the second source and drain regions 6b and 7b in the peripheral region PR, respectively. A metal film is formed over the fourth insulating layer 24 to be buried with the first and the second metal contact holes 25 and 26 and then patterned to form a first and a second metal interconnections 27 and 28 which are contacted with the second source region 6b and the drain region 7b in the peripheral region PR, respectively.
The prior SOI device with a RSC cell structure has low junction capacitance as it is, as like a conventional SOI device and prevents the global topology from occurring in forming a capacitor, so that metal contact holes in the peripheral region are formed with easy and reliability of metal interconnections are assured.
However, because a body of a transistor in the prior SOI device is floated, floating body effect such as parasitic bipolar junction transistor(BJT) effect and kink effect is occurred so that device characteristic is degraded.
It is an object of the present invention to provide a SOI device for preventing floating body effect from occurring and a method for fabricating the same.
According to an aspect of the present invention, there is provided to a silicon-on-insulator (SOI) device, comprising: a semiconductor layer having a constant thickness, including a cell region and a peripheral region; an isolation film of a trench type formed in one surface of the semiconductor layer at a lower depth than the thickness of the semiconductor layer to define device formation regions in the cell region and the peripheral region; a first and a second gates formed over the one surface of the semiconductor layer in the device formation regions of the cell region and the peripheral region which are defined by the isolation film, respectively; first source and drain regions formed in the device formation region at the both sides of the first gate in the cell region and second source and drain regions formed in the device formation region at the both sides of the second gate in the peripheral region; a first insulating layer formed over the one surface of the semiconductor layer to cover the first and the second gates; a capacitor formed over the first insulating layer to be contacted with the first source region in the cell region; a second insulating layer formed over the first insulating layer to cover the capacitor; a supporting substrate bonded on the second insulating layer; a first impurity region formed in another surface of the semiconductor layer over the first drain region in the cell region to be contacted with the first drain region; a second and a third impurity regions formed in the another surface of the semiconductor over the second source and drain regions in the peripheral region to be contacted with the second source and drain regions, respectively; a third insulating layer formed on the another surface of the semiconductor layer; a first contact hole formed in the third insulating layer to expose the first impurity region; a bit line formed over the third insulating layer to be contacted with the first impurity region through the first contact hole; a fourth insulating layer formed over the third insulating layer to cover the bit line; a second and a third contact holes formed in the third and the fourth insulating layers to respectively expose the second and the third impurity regions; and a first and a second metal interconnections formed over the fourth insulating layer to be connected with the second and the third impurity regions through the second and the third contact holes, respectively.
There is also provided to a method for fabricating a silicon-on-insulator (SOI) device, comprising the steps of preparing a semiconductor substrate having a cell region and a peripheral region; forming an isolation film of a trench type in one surface of the semiconductor substrate to define device formation regions in the cell region and the peripheral region, the isolation film having a constant depth; forming first and second gates in the device formation regions of the cell region and the peripheral region defined by the isolation film, respectively; forming first source and drain regions in the device formation region at the both sides of the first gate in the cell region and the second source and drain regions in the device formation region at the both sides of the second gate in the peripheral region; forming a first insulating layer over the one surface of the semiconductor substrate to cover the first and the second gates; forming a capacitor over the first insulating layer to be contacted with the first source region in the cell region; forming a second insulating layer over the first insulating layer to cover the capacitor; bonding a supporting substrate on the second insulating layer; polishing another surface of the semiconductor substrate to form a semiconductor layer having a thicker thickness than the depth of the isolation film; forming a third insulating layer over the semiconductor layer; etching the third insulating layer to expose a portion of the semiconductor layer over the first drain region in the cell region; forming a first impurity region in an exposed portion of the semiconductor layer to be contacted with the first drain region in the cell region; forming a bit line over the third insulating layer to be electrically contacted with the first impurity region of the cell region; forming a fourth insulating layer over the third insulating layer to cover the bit line; etching the third and fourth insulating layers to expose portions of the semiconductor layer over the second source and drain regions in the peripheral region, respectively; forming a second and a third impurity regions exposed portions of the semiconductor layer to be contacted with the second source and drain regions in the peripheral region, respectively; and forming a first and a second metal interconnections over the fourth insulating layer to be electrically contacted with the second and third impurity regions in the peripheral region, respectively.